The centralized architecture of the Cisco 10000 Series Router enables a simplified, cost-competitive SIP design that delivers all of the advanced hierarchical QoS (HQoS), high availability, scalability, and forwarding capabilities of the PREs to a wide range of SPA interfaces for maximum flexibility and price/performance.
The Cisco 10000 Series SIP-600 supports four single-height or two double-height SPAs using two adjacent line-card slots of the Cisco 10000 Series Router. Using application-specific integrated circuits (ASICs) and the flexibility to bond together point-to-point links, the SIP provides up to 11.2 Gbps of bandwidth and support for 10 Gigabit Ethernet interface at line-rate.
SPA modularity greatly extends the port density on the current Cisco 10000 Series chassis and offers customers flexible interface deployment options, making the Cisco 10000 Series Router an ideal choice for service provider customers who need high-density aggregation at the edge with the ability to share next-generation interfaces across multiple Cisco platforms.
Increased port density, bandwidth, and SPA support
Supports 4 single-height SPAs, 2 double-height SPAs, or a combination to increase port density per chassis. Link bonding enables greater bandwidth and new connectivity options such as a modular 10GE SPA.
Provides support for up to 4 SIPs or a combination of SIPs plus older Cisco 10000 Series line cards installed in the same chassis.
Same carrier card is used for various SPA types supported on the Cisco 10000 Series Router. In addition, SPA interfaces can be shared across multiple platforms.
Online Insertion and Removal (OIR)
Provides hitless OIR to minimize impact of add, change, and remove operations. Individual SPAs can be removed without impacting traffic on other SPA interfaces.
Link protection and link bundling
Ethernet - 802.3ad, Cisco EtherChannel technology. SONET - Automatic Protection Switching (APS)
Hierarchical QoS provided on PRE3 and PRE4 allows oversubscription of interfaces with predictable performance. SIP memory includes 128MB buffering to support ingress bursts of 20 Gbps for 50 ms.
Building Integrated Timing Supply (BITS)
Supports BITS-enabled SPAs.